1. Field of the Invention
This invention relates to double diffused MOS (DMOS) transistors and more particularly to an improved power DMOS transistor.
2. Description of Prior Art
A DMOS transistor is one in which the difference in the diffusion boundaries of sequentially introduced impurities is used to define channel length. FIG. 1 is a cross-sectional diagram of a lateral DMOS transistor constructed in accordance with the prior art. Transistor 10 of FIG. 1 includes N+ type drain region 12d diffused into N type substrate 14, P+ body region 16, and N+ type source region 12s located within P+type body region 16. Located above a portion of P+ type body region 16 is a layer of gate insulation 18, and above gate insulation 18 is polycrystalline silicon gate 12g. Field oxide layer 19 provides insulation and a protective layer for the device. Illustrated in FIG. 1 are metal contacts 22, 24. Metal contact 24 makes electrical connection to source region 12s and body region 16 while metal contact 22 makes electrical connection to drain 12d. A third metal contact (not shown) makes electrical contact to polycrystalline silicon gate 12g. As is well-known in the art, when a voltage above the threshold voltage of transistor 10 is applied to gate 12 g, an N type channel is created in P+ type body region 16 under gate 12g, and current can flow between source 12s and drain 12d. Source 12s, body region 16, and drain 12d correspond respectively to the emitter, base, and collector of a parasitic bipolar transistor. Accordingly, in an attempt to prevent turn-on of the parasitic bipolar transistor during operation of the DMOS transistor 10, source 12s and body region 16 are normally shorted together by means of an ohmic connection, such as metal contact 24. DMOS transistors such as that shown in FIG. 1 are especially useful in conducting higher currents due to the short channel length. U.S. Pat. No. 4,300,150 to Colak further describes this lateral DMOS transistor and is incorporated by reference.
A prior art variation of the transistor of FIG. 1 is illustrated in FIG. 2. FIG. 2 shows transistors 48, 50, which include N+type substrate 52 serving as a drain, located below a more lightly doped N type epitaxial layer 54. Within N type layer 54 is P+ type deep body region 56 and P type region 57. Within body region 57 are N+ source regions 58, 60. Between the diffusion boundaries of source regions 58, 60 and body region 57 are channel regions 61, 63, and overlying channel regions 61, 63, is gate insulation 62, 64. Above gate insulation 62, 64 are polycrystalline silicon gates 66, 68. When voltage applied to gates 66, 68 is above the threshold voltage of transistors 48, 50, current can flow between drain 52 and source regions 58, 60. Metal contact, 70 makes ohmic contact to source regions 58, 60 and deep body region 56, and a gate contact (not shown) makes ohmic contact to gates 66, 68. These transistors are known as vertical DMOS transistors.
As is well-known in the art, when a positive voltage above the threshold voltage of transistors 48, 50 is applied to gates 66, 68 of transistors 48, 50, a thin N type conductive channel is created in channel regions 61, 63 just below gates 66, 68. The more positive the gate voltage, the thicker this conductive channel becomes and the more working current flows. Current flows horizontally near the surface between source regions 58, 60 and epitaxial layer 54, and then vertically through epitaxial layer 54 and drain 52.
A typical use of a vertical DMOS transistor is as a switching device or speed control for a motor, or as a switching device in power conversion equipment. When a DMOS transistor, used with an inductive load, is rapidly turned off, the large dV/dt due to the rapid turn-off of the DMOS transistor causes an oscillation or transient to be generated in the circuit due to the LC circuit created by the combination of the inductive load with the capacitances throughout the circuit and parasitic capacitances in the DMOS transistor itself. This transient voltage can cause turn-on of the DMOS transistor if the voltage between the source and the drain forward biases the body diode within the DMOS transistor. The body diode is formed by the P-N junction between P+ type deep body region 56, or P type body region 57, and N type layer 54, shown in FIG. 2. (This forward bias voltage can be generated in a number of ways depending on the usage of the transistor.) The now supposedly "off" DMOS transistor is conducting until the voltage reverses and the body diode is no longer forward biased. Further, if the voltage swing is fast enough, it can turn on the parasitic bipolar junction transistor (BJT) formed by the N+ type source, the P+ type body, and the N type epitaxial layer. If sufficient current is drawn through the BJT, avalanche breakdown or second breakdown of the BJT may occur, potentially resulting in catastrophic failure of the DMOS transistor. FIG. 3 shows a simplified equivalent circuit within the structure of a power DMOS transistor showing the various capacitances in the transistor and the parasitic BJT. The body diode in FIG. 3 is the base-collector junction of the parasitic BJT. Also shown in FIG. 3 is gate-drain capacitance C.sub.gd, gate-source capacitance C.sub.gs, drain-body capacitance C.sub.db, body-source capacitance C.sub.bs, body-resistance R.sub.b, body-todrain resistance R.sub.d, and epitaxial resistance R.sub.epi. FIG. 4 shows an equivalent circuit to that shown in FIG. 3.
When the body diode is forward biased, minority carriers are injected into the P and N junctions of the body diode, thus increasing the recovery time of the body diode when it changes abruptly from the forward bias state to the reverse bias state. This causes the DMOS transistor to conduct current for an even longer time after it has been supposedly shut off. Some prior art DMOS transistors have modified the P-N body diode such that the minority carriers have a lower lifetime, thus decreasing recombination time, however, this modification increases the resistance of the P type and N type material and complicates the processing sequence
This dV/dt turn-on may be avoided in many ways. One way is to introduce an external silicon diode in parallel with the DMOS transistor, and a low voltage Schottky diode in series with the DMOS transistor, so that only the diode in parallel will conduct current, thus diverting current from flowing through the body diode. This circuit is shown in FIG. 5. Using this circuit, however, incurs a penalty in the power cost of the series diode and the extra cost of both external diodes. All methods known to the Applicant which bypass current around the body diode use external components.
Siliconix Technical article TA84-4, entitled "dV.sub.ds /dt Turn-On in MOSFETs", by Rudy Severns, dated April 1984, discusses modes of dV/dt turn-on in detail and is incorporated by reference. The article "Power MOSFET Ruggedness Testing and Performance" by Peter J. Carlson in PCIM, October 1986, provides more details on dV/dt turn-on and is also incorporated by reference.